With the rapid growth of Ethernet in the field of networking, the number of systems using PoE (ethernet power supply) on 10/100 and GB ports is also increasing rapidly. The benefits and cost advantages of supplying power to remote devices via Ethernet cables enable many applications (including IP telephony, digital video surveillance, WLAN access points and other low-voltage network connection systems) to be implemented.
Typical PoE systems use power supply equipment (PSE) to send DC voltage to remote receiving equipment (PD) via Ethernet twisted pair. As PoE system is often threatened by transient voltage, one of the important issues to be considered in design is to protect the physical layer transceiver (PHY) of Ethernet from overvoltage impact.
With the growth of PoE applications, the size of Ethernet PHY is shrinking rapidly. At present, Ethernet PHY is mostly manufactured using 90-nm technology, but chip manufacturers will soon introduce smaller products manufactured using 65-nm technology. Facts show that it is impractical to implement effective chip-level ESD protection in CMOS with these advanced manufacturing technologies, because the chip area is too small to provide system-level robustness, and the cost of achieving effective chip-level protection is too high. In order to meet the requirements of global standards and ensure the reliability of the system, the current system design based on Ethernet is increasingly demanding better off-chip circuit protection.
Transient Voltage Threat
Ethernet interface is vulnerable to various transient overvoltage events, the most common of which are electrostatic discharge (ESD), cable discharge and lightning surge. In addition, in PoE system, the transmission of DC power through twisted pair leads to some special transient faults caused by differential mode connection.
ESD is a very fast transient pulse. According to the model given by IEC61000-4-2 standard, the rise time of ESD waveform is 700 picoseconds to 1 nanosecond, and the pulse duration from peak current to 50% is 60 nanoseconds. Large current spikes and transient energy may damage the submicron input structure of silicon chips.
Cable discharge (CDE), or cable electrostatic discharge (CESD), occurs when the Ethernet cable is charged under the conventional environment such as friction charged effect or induction. It is dangerous to insert live cables into the system interface. The fact shows that the cable discharges to the Ethernet port through the Ethernet magnetic channel will form several different modes of surges. Similar to ESD, the rise time of cable discharge surge is very short (less than 1 nanosecond), but unlike ESD, the secondary waveform oscillates rapidly and lasts a long time. For Ethernet designers, the energy in cable discharge waveforms can cause more serious problems than human electrostatic discharge.
Lightning surge is a common threat in network connection. Lightning shocks can generate high-voltage pulses that may be transmitted to Ethernet PHY over the Ethernet line. Unlike nanosecond ESD events, lightning surges last for milliseconds. The EMC industry describes such pulses in terms of rise time (milliseconds), peak pulse current and fall time. The energy of lightning shock is several orders of magnitude larger than that of ESD shock.
Differential Mode Transient Response in PoE Applications
As mentioned earlier, the protection of the PoE interface can be particularly challenging, because in addition to the transient process caused by ESD and surge, there are several common situations that can cause differential surges on the Ethernet transmission line when connecting to DC power. This will naturally cause disastrous failures or problems for PHY, and severe shocks may damage IC.
Most PoE circuit designers take some form of common-mode protection to protect the PoE circuit. Common-mode capacitors connected to the ground or TVS Transient Voltage Suppressors connected to both ends of the power supply, which rely on very fast Schottky diodes to direct current to the ground, are commonly used. However, many designers mistakenly ignore differential mode protection. The differential pair of Ethernet isolates PHY from the external environment using transformers or common mode current repression. Transformers can provide high level common-mode isolation for external voltages, but cannot provide protection for metallic or differential (line-to-line) surges.
PoE system has a voltage of + 48V or - 48V on differential pair. In signal line alignment, this DC voltage is public, so the differential DC voltage is 0 volts. However, in some cases, the connection may introduce transient processes.
For example, pin engagement may not occur synchronously when RJ-45 connections are made between power supply equipment and power receiving equipment. When pin contacts RJ-45, pin 1 may occur earlier or later than pin 2. This will result in a differential transient process of 48V on the line pair, which will damage or damage the PHY of the PoE circuit. Similar situations occur when a user switches a connection from an already powered device to an unpowered device at the same power port. When the power supply device detects that an unpowered device has been connected, there will be a delay when the power supply device terminates the power supply to the former. In this case, the power can last long enough to form a 48V differential voltage by non-simultaneous connection of pins. The differential mode transient caused by this situation may damage or damage PHY.
Transient Voltage Suppression (TVS) Diodes
Obviously, because the PoE structure is exposed to harsh environmental threats, it needs to be protected by off-chip circuits. Low voltage TVS diode is a mature protection technology for Ethernet transceiver. The diode has fast response (sub-nanosecond level), low capacitance and low clamping voltage, and is very suitable for resisting various transient surges.
In order to provide differential protection for PoE circuits, an effective TVS diode protection scheme must be able to clamp the transient/surge and present the smallest load capacitance on the interface. TVS should provide low clamp voltage and, as a general rule, line-to-line capacitance should not exceed several skin methods. In addition, as a unique requirement of PoE circuit, TVS configuration must consider the existence of +/-48V DC voltage between on-line pairs. Because of the high DC voltage between different pairs of wires, integrated diode arrays or bridge TVS devices that form electrical paths between any pairs of wires can not be used. Differential pairs must be electrically isolated.
An example of POE TVS scheme implemented by Semtech RClamp 0524S to resist differential mode transient is given. In the implementation of PoE protection circuit, there are some advantages of putting the protection circuit on the power supply side: it can not only protect the downstream power switch circuit, but also avoid the transient current flowing through the transformer. Since any additional inductance increases the ESD clamp voltage of the TVS diode, TVS should be as close to the connector as possible. The TVS arrays in this example have small inter-line capacitance, and since these diode pairs are separated in the package, they also provide the necessary line isolation to isolate the 48V voltage between differential pairs. In addition, the flow-through layout shown in Figure 3 reduces the total inductance in the transient path and facilitates the PCB layout.